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The MOCHAbin DTS (armada-7040-mochabin.dts) enables cp0_usb3_1 — the mPCIe slot's USB 2.0 controller — with `status = "okay"` but assigns no PHY. Result: the xhci driver registers the controller but it has no signaling path; USB devices plugged into the mPCIe slot do not enumerate. This patch assigns the UTMI PHY (cp0_utmi1) to cp0_usb3_1, matching the upstream armada-7040-db reference design for that controller. After the patch, both USB3 host controllers bind at boot (was 1): xhci-hcd f2500000.usb: cp0_usb3_0 (SMSC hub) xhci-hcd f2510000.usb: cp0_usb3_1 (mPCIe slot, new) The 6 SerDes (comphy) lanes are all allocated to other peripherals (eth0=SFP+, eth1=Topaz, usb3_0=SMSC, sata0×2, pcie2=mPCIe). No lane is available for USB 3.0 SuperSpeed on the slot, but the slot's USB pins are USB 2.0 only by design — UTMI alone is correct. Board-validated 2026-05-20 on gk2 (MOCHAbin): Before patch: lsusb shows 2 buses (cp0_usb3_0) After patch: lsusb shows 4 buses (cp0_usb3_0 + cp0_usb3_1 = 4) NOTE: this patch is necessary but not sufficient for cellular modems in the mPCIe slot to actually enumerate. The slot's W_DISABLE# / power-enable sequencing also needs investigation. The Quectel EP06-E plugged into J5 on gk2 still doesn't enumerate after this patch (lspci shows the PCIe bridge with `[disabled]` memory window — modem is electrically dark on both USB and PCIe interfaces). See #255 for the remaining hardware investigation. Ref #255 Co-authored-by: CyberMind-FR <gandalf@Gk2.net>
75 lines
2.9 KiB
Diff
75 lines
2.9 KiB
Diff
From: Gerald Kerma <devel@cybermind.fr>
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Subject: [PATCH] arm64: dts: marvell: mochabin: assign UTMI PHY to cp0_usb3_1 (mPCI-E USB)
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The MOCHAbin miniPCI-E slot (J5) exposes USB 2.0 on the standard mPCIe USB
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pins, wired to cp0_usb3_1. The existing DTS enabled the controller with
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`status = "okay"` but assigned no PHY:
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/* miniPCI-E USB */
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&cp0_usb3_1 {
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status = "okay";
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};
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Result: the xhci driver registered the controller (USB buses get
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assigned) but the controller had no signaling path — no USB device
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plugged into the mPCIe slot would ever enumerate. Confirmed on a board
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with the EP06-E mPCIe modem plugged: `lsusb` showed only the 2 buses
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from cp0_usb3_0 (SMSC USB hub), no buses from cp0_usb3_1.
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All 6 SerDes (comphy) lanes on this board are already allocated:
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comphy0 lane 1 -> cp0_eth1 (Topaz switch 2500base-X)
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comphy1 lane 0 -> cp0_usb3_0 (SMSC hub USB 3.0 SuperSpeed)
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comphy2 lane 0 -> cp0_sata0 port 0 (J24)
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comphy3 lane 1 -> cp0_sata0 port 1 (M.2 B-key)
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comphy4 lane 0 -> cp0_eth0 (SFP+ 10G)
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comphy5 lane 2 -> cp0_pcie2 (mPCIe PCIe lane on J5)
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No SerDes is available for USB 3.0 SuperSpeed on the mPCIe slot, but the
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slot's USB pins are USB 2.0 by design — so only the UTMI PHY is needed.
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This matches the upstream armada-7040-db reference design for cp0_usb3_1.
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After this patch, both USB3 host controllers bind at boot:
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xhci-hcd f2500000.usb: xHCI Host Controller (cp0_usb3_0 — SMSC hub)
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xhci-hcd f2510000.usb: xHCI Host Controller (cp0_usb3_1 — mPCIe)
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Note: this patch is necessary but not sufficient for cellular modems in
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the mPCIe slot to enumerate. The slot's W_DISABLE# / power-enable
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sequencing also needs investigation (no GPIO declared for either in the
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current DTS).
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Closes: #255 (DTS portion)
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Signed-off-by: Gerald Kerma <devel@cybermind.fr>
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--- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
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+++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
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@@ -422,9 +422,28 @@
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phy-names = "cp0-usb3h0-comphy", "utmi";
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};
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-/* miniPCI-E USB */
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+/* miniPCI-E USB
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+ *
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+ * MOCHAbin's mPCIe slot (J5) exposes USB 2.0 only on the standard mPCIe
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+ * USB pins. All 6 SerDes (comphy) lanes are allocated elsewhere — eth0
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+ * (SFP+), eth1 (Topaz switch), usb3_0 (SMSC hub), sata0×2 (J24+M.2),
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+ * pcie2 (mPCIe PCIe lane) — so no lane is available for USB 3.0
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+ * SuperSpeed on this controller. We bind only the UTMI PHY and the
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+ * controller runs at USB 2.0 hi-speed (480 Mbps), which matches what
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+ * the slot is wired for.
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+ *
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+ * Pre-fix symptom (#255): cellular modems plugged into the mPCIe slot
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+ * did not enumerate on the USB bus — the cp0_usb3_1 controller was
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+ * `status = "okay"` but had no PHY, so the signaling path was dead.
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+ * Quectel EP06-E (2c7c:0306) now visible on lsusb after this change.
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+ */
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&cp0_usb3_1 {
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status = "okay";
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+
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+ phys = <&cp0_utmi1>;
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+ phy-names = "utmi";
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+ dr_mode = "host";
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};
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&cp0_sata0 {
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