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https://github.com/CyberMind-FR/secubox-deb.git
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b1ebae2d58
The MOCHAbin DTS (armada-7040-mochabin.dts) enables cp0_usb3_1 — the mPCIe slot's USB 2.0 controller — with `status = "okay"` but assigns no PHY. Result: the xhci driver registers the controller but it has no signaling path; USB devices plugged into the mPCIe slot do not enumerate. This patch assigns the UTMI PHY (cp0_utmi1) to cp0_usb3_1, matching the upstream armada-7040-db reference design for that controller. After the patch, both USB3 host controllers bind at boot (was 1): xhci-hcd f2500000.usb: cp0_usb3_0 (SMSC hub) xhci-hcd f2510000.usb: cp0_usb3_1 (mPCIe slot, new) The 6 SerDes (comphy) lanes are all allocated to other peripherals (eth0=SFP+, eth1=Topaz, usb3_0=SMSC, sata0×2, pcie2=mPCIe). No lane is available for USB 3.0 SuperSpeed on the slot, but the slot's USB pins are USB 2.0 only by design — UTMI alone is correct. Board-validated 2026-05-20 on gk2 (MOCHAbin): Before patch: lsusb shows 2 buses (cp0_usb3_0) After patch: lsusb shows 4 buses (cp0_usb3_0 + cp0_usb3_1 = 4) NOTE: this patch is necessary but not sufficient for cellular modems in the mPCIe slot to actually enumerate. The slot's W_DISABLE# / power-enable sequencing also needs investigation. The Quectel EP06-E plugged into J5 on gk2 still doesn't enumerate after this patch (lspci shows the PCIe bridge with `[disabled]` memory window — modem is electrically dark on both USB and PCIe interfaces). See #255 for the remaining hardware investigation. Ref #255 Co-authored-by: CyberMind-FR <gandalf@Gk2.net> |
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| 001-leds-is31fl319x-add-i2c-delays.patch | ||
| 002-i2c-mv64xxx-increase-errata-delay.patch | ||
| 003-mochabin-mpcie-usb-phy.patch | ||